1. Field of the Invention
This invention relates to a matrix-addressed display device that displays for example a TV picture, more particularly to the construction of a sampling frequency genertor in serial-parallel conversion by sampling the input picture signal.
2. Background of the Prior Art
Recent years have witnessed rapid advances in the technology of TV picture display terminals employing matrix-addressed display elements using liquid crystals, and some of these advances have reached the stage of being utilized in practice. In such matrix-addressed display devices, the video signal has to be supplied to a large number of signal lines and sampling used to perform serial-parallel conversion on the TV signal etc., which is in the form of a dot-sequential signal.
"Serial-parallel conversion"38 means that serial data, i.e. data that is time-serially transmitted on a single transmission line, is converted to parallel data that is simultaneously transmitted on a plurality of transmission lines. Such serial-parallel conversion is utilized in a matrix-addressed display device that is driven by one-line-at-a-time addressing.
A typical matrix-addressed liquid crystal display device has a rectangular display panel consisting of thin film transistors (TFT) arranged in a matrix constituted by the points of intersection of respective signal lines X1, . . . , Xm and address lines Y1, . . . , Yn, which are provided in the horizontal direction (X axis direction or main addressing direction) and vertical direction (Y axis direction or ancillary addressing direction). To display a picture, the temporarily stored serial picture signal is supplied in parallel to all of the signal lines X1 . . . Xm, simulataneously, and then selected and displayed by the address lines Y1 . . . Yn, Each scan of the address lines gives one picture frame.
To operate this matrix display, a picture signal source, frame inverting amplifier, synchronizing signal separator, control circuit, Y driver and X driver are arranged around the periphery of the display panel. The X driver is provided with a sampling pulse generator and sample and hold circuit. The picture elements within the liquid crystal display panel are constituted by a TFT, a signal storage capacitor, a liquid crystal cell and a counter electrode common to all the picture elements.
FIG. 6 is a waveform diagram given in explanation of the operation of such a display device. a and b are respectively the vertical synchronizing signal and horizontal synchronizing signal obtained at the output of the synchronizing signal separator. c is the vertical scanning start signal. This is generated under the control of the abovementioned synchronizing signals. Horizontal synchronizing signal b and vertical scanning start signal c are fed to the Y driver to address, one line at a time, the address lines Y1, . . . , Yn of the liquid crystal display panel. Also d is the picture signal. This is supplied from the picture signal source through the frame inverting amplifier to the sample and hold circuit. The drawing shows the period of a single horizontal scan. e1 and f are respectively the sampling frequency signal and horizontal scanning start signal. These signals are generated under the control of the horizontal synchronizing signal b. It should be noted that, in the Figure, the length of the time axis of the other signals shown below signal d is the same as in the case of signal d itself.
Of these, the sampling frequency signal e1 and the horizontal scanning signal f are supplied to the sampling pulse generator, which is constituted by a shift register, and generates sampling pulses S1, . . . , Sm. These sampling pulses S1, . . . , Sm are supplied to the sample and hold circuit, which converts the picture signal d into a parallel picture signal by a sequential sample-and-hold operation performed with the period of the horizontal scanning. When this conversion is completed, the parallel picture signal is simultaneously delivered, under the control of output enable pulse g from the control circuit, from the sample and hold circuit to the signal lines X1, . . . , Xm of the liquid crystal panel. This causes the picture signal voltage to be written from the signal lines X1, . . . , Xm into the signal storage capactiors, through those TFT which are in an on-state as a result of one or other of the address lines Y1, . . . , Yn having been put into the selected state by the vertical scanning pulse from the Y driver. The picture is displayed by excitation of the liquid crystal cells by the picture signal voltage, which is held for the frame scanning period.
However, in the prior art display device, the sampling frequency generator is provided in the control circuit. FIG. 7 shows the construction of a frequency synthesizer in which a PLL (Phase-Locked Loop) is utilized as this sampling frequency generator. As shown in FIG. 7, this sampling frequency generator is composed of a voltage controlled oscillator 10, a counter 11, a phase comparator 12, a low pass filter 13, a reference frequency input terminal 14 and an oscillating frequency output terminal 15. By setting the count of counter 11 to a desired value, for example K, this enables a frequency of K times the horizontal synchronizing frequency, as shown in e1 of FIG. 6, to be obtained at oscillating frequency output terminal 15 when the horizontal synchronizing signal shown at b of FIG. 6 is supplied to reference frequency input terminal 14.
However, with a matrix-addressed display device as described above, if the sampling frequency generator is constructed of a PLL, fine picture display is difficult to obtain, due to disturbances of the sampling timing resulting from frequency or phase instability of the oscillating output pulse. Futhermore, power is consumed unnecessarily by the fact that the oscillating pulse from the samplng frequency pulse generator is outputted continuously, even during periods wherein a sampling pulse is not required, such as the period where the output enable pulse g of FIG. 6 is high-level.